负电容场效应晶体管在存储器领域应用的研究进展-物理科学与技术研究-科技核心数据库

相关机构

负电容场效应晶体管在存储器领域应用的研究进展

Research progress of negative capacitance field effect transistor in memory field

被引量： ES评分0 浏览量：131

全文阅读下载引用收藏

DOI	10.12208/j.pstr.20230002
刊名	物理科学与技术研究 Physical Sience and Technical Research
年，卷(期)	2023, 3(1)
作者	张冲^1,2,蔡亚丽^1,2,于子苇²,岳文峰^1,2,3,俞亮^1,2,3,郭全胜¹,贾婷婷^1,2,
作者单位	1 湖北大学材料科学与工程学院湖北武汉 ; 2 中国科学院深圳先进技术研究院先进材料科学与工程研究所广东深圳 ; 3 中国科学技术大学纳米学院江苏苏州 ;
摘要	近年来，随着便携电子设备及数据中心对内存存储需求的持续扩大，提升存储性能的创新方案备受研究关注。其中，负电容场效应晶体管（Negative Capacitance Field Effect Transistor （NCFET））作为一种存储性能得以改进的方案受到广泛关注。NCFET采用铁电材料作为晶体管中的电容层，通过实现负电容行为以操作通道中的电荷载流子。已有研究证明，NCFET的负电容行为能够在速度、稳定性和耐用性方面对存储器性能进行改善。本文全面回顾了NCFET在电子领域的研究现状，包括基本原理、所使用的材料、最新进展以及在数字和模拟集成电路中的应用。最后，文章探讨了实施NCFET在存储技术中所面临的挑战以及潜在的解决方案。 In recent years, as the demand for memory storage in portable electronic devices and data centers continues to expand, innovative solutions to improve storage performance have received much research attention. Among them, negative-capacitance field-effect transistors (NCFETs) have received much attention as a solution to improve memory performance. NCFETs use ferroelectric materials as the capacitive layer in the transistor to operate the charge carriers in the channel by implementing negative-capacitance behavior. It has been demonstrated that the negative capacitance behavior of NCFETs can improve memory performance in terms of speed, stability, and endurance. This paper provides a comprehensive review of NCFET research in electronics, including the fundamentals, materials used, recent advances, and applications in digital and analog integrated circuits. Finally, the article explores the challenges and potential solutions for implementing NCFETs in storage technology.
关键词	负电容场效应晶体管；数字电路；模拟电路；存储电路 Negative capacitance field effect transistors; Digital circuits; Analog circuits; Memory circuits
基金项目
页码	13-20

参考文献
相关文献

[1] A. M. Ionescu, "TWO-DIMENSIONAL MATERIALS Negative capacitance gives a positive boost," Nat Nanotechnol, vol. 13, no. 1, pp. 7-8, Jan. 2018.

[2] H. Lee, Y. Yoon, and C. Shin, "Current-Voltage Model for Negative Capacitance Field-Effect Transistors," Ieee Electr Device L, vol. 38, no. 5, pp. 669-672, May. 2017.

[3] S. Gupta, M. Steiner, A. Aziz, V. Narayanan, S. Datta, and S. K. Gupta, "Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic," Ieee Transactions on Electron Devices, vol. 64, no. 8, pp. 3092-3100, Aug. 2017.

[4] M. Hoffmann, P. V. Ravindran, and A. I. Khan, "Why Do Ferroelectrics Exhibit Negative Capacitance?," Materials (Basel), vol. 12, no. 22, Nov 13. 2019, DOI: 10.3390/ma12223743.

[5] 9S. George et al., "Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors," in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 11-13 July 2016. 2016, pp. 649-654.

[6] M. A. Alam, M. Si, and P. D. Ye, "A critical review of recent progress on negative capacitance field-effect transis-tors," Appl Phys Lett, vol. 114, no. 9, pp. 090401, 2019/03/04. 2019.

[7] A. Aziz, S. Ghosh, S. Datta, and S. K. Gupta, "Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors," Ieee Electr Device L, Articlevol. 37, no. 6, pp. 805-808, 2016 JUN. 2016.

[8] 9M. H. Lee et al., "Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies," in 2015 IEEE International Electron Devices Meeting (IEDM), 7-9 Dec. 2015. 2015, pp. 22.5.1-22.5.4.

[9] 9A. Aziz et al., "Computing with ferroelectric FETs: Devices, models, systems, and applications," in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 19-23 March 2018. 2018, pp. 1289-1298.

[10] S. Guha and P. Pachal, "Heterojunction Negative-Capaci-tance Tunnel-FET as a Promising Candidate for Sub-0.4V V-DD Digital Logic Circuits," Ieee T Nanotechnol, Articlevol. 20, pp. 576-583, 2021. 2021.

[11] S. Mehrotra and S. Qureshi, "Performance Considerations of Thin Ferroelectrics (~10 nm HfO2, ~20 nm PZT) FDSOI NCFETs for Digital Circuits at Reduced Power Consumption
[arXiv]," arXiv, Journal Paperpp. 8 pp.-8 pp., 2019 06 12. 2019.

[12] 4L. Chia-Chen, W. Yi-Jui, Y. Wei-Xiang, and S. Pin, Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers (2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)). 2020, pp. 62-3.

[13] X. Z. Yin, D. Reis, M. Niemier, and X. S. Hu, "Ferroelectric FET based TCAM Designs for Energy Efficient Computing," 2019 Ieee Computer Society Annual Symposium on Vlsi (Isvlsi 2019), pp. 438-443, 2019.

[14] R. Islam, "Negative Capacitance Clock Distribution," IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, Articlevol. 9, no. 1, pp. 547-553, 2021 JAN 1. 2021.

[15] T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits," Ieee Electr Device L, vol. 39, no. 1, pp. 147-150, 2018.

[16] 9S. George et al., "NCFET Based Logic for Energy Harvesting Systems," 2015.&

[17] S. Salamin, G. Zervakis, Y. S. Chauhan, J. Henkel, and H. Amrouch, "PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4299-4309, 2021.

[18] Y. Liang, Z. Zhu, X. Li, S. K. Gupta, S. Datta, and V. Narayanan, "Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances," Ieee T Vlsi Syst, Articlevol. 27, no. 12, pp. 2855-2860, 2019 DEC. 2019.

[19] G. Paim et al., "On the Resiliency of NCFET Circuits Against Voltage Over-Scaling," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 4, pp. 1481-1492, 2021.

[20] H. Eslahi, T. J. Hamilton, and S. Khandelwal, "Small signal model and analog performance analysis of negative capacitance FETs," Solid State Electron, vol. 186, pp. 108161, 2021/12/01/. 2021.

[21] D. Reis, M. Niemier, and X. S. Hu, "Computing in memory with FeFETs," I Sympos Low Power E, pp. 134-139, 2018.

[22] X. Z. Yin, K. Ni, D. Reis, S. Datta, M. Niemier, and X. B. S. Hu, "An Ultra-Dense 2FeFET TCAM Design Based on a Multi-Domain FeFET Model," Ieee T Circuits-Ii, vol. 66, no. 9, pp. 1577-1581, Sep. 2019.

[23] A. F. Laguna, M. Niemier, and X. S. Hu, "Design of Hardware-Friendly Memory Enhanced Neural Networks," Des Aut Test Europe, pp. 1583-1586, 2019.

[24] Y. Hong, Y. Choi, and C. Shin, "NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity," IEEE Transactions on Electron Devices, vol. 8, no. 1, pp. 182-188, 2020.

[25] C. Liu et al., "Hf0.5Zr0.5O2-Based Ferroelectric Field-Effect Transistors With HfO2 Seed Layers for Radiation-Hard Nonvolatile Memory Applications," Ieee Transactions on Electron Devices, vol. 68, no. 9, pp. 4368-4372, Sep. 2021.

[26] C. Mitchell, C. L. McCartney, M. Hunt, and F. D. Ho, "Characteristics of a Three-Transistor DRAM Circuit Utilizing a Ferroelectric Transistor," Integr Ferroelectr, ArticleProceedings Papervol. 157, no. 1, pp. 31-38, 2014. 2014,.

[27] G. Hota and A. Raychowdhury, "A Time-based ADC for Read-Modify-Write in Ferroelectric-FET Based Pseudo-Crossbar Arrays," Asia Pac Conf Postgr, pp. 9-12, 2019.

相关学者

相关机构